1. The Field of the Invention
This invention generally relates to semiconductor integrated circuit memory structures and, more precisely, relates to a memory array having global array bit lines each of which is connected hierarchically above a plurality of electrically isolatable subarray bit lines, each subarray bit line being connected hierarchically above a plurality of memory cells, each memory cell being in communication with a corresponding word line, where data can be left floating and can be refreshed in temporary storage on both the global array bit lines and the electrically isolatable subarray bit lines which have sufficient capacitance to maintain readily accessible data in temporary storage.
2. The Relevant Technology
In dynamic random access memory chips, bit line capacitance is an important consideration. A reduction in bit line capacitance reduces the amount of power required by the memory cell structure. Attempts have been made to optimize or maintain the overall cell capacitance to bit line capacitance ratio. In the past, efforts to maintain the cell capacitance to bit line capacitance ratio have been made by segmenting the bit line array and by adding more N-sensamps, P-sensamps, and/or more column decodes. While such additional structure makes progress toward maintenance of the cell capacitance to bit line capacitance ratio, these gains are made at a cost of adding expensive overhead to the memory chip, as well as reducing the efficiency of the memory chip. In addition to the forgoing problems in the prior art, a need exists to improve the temporary data storage capability of high density memory array structures so as to increase the efficiency of data storage without increasing circuitry overhead for such temporary data storage.